E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.5.8. Steps to Disable FEC

The following steps provide a procedure for disabling FEC for the 100G variant. For actual software implementation of the various steps, please refer to the software routines in the Design Example:
  1. FEC disabling:
    1. Bypass FEC - Write 0x0000 to FEC register 0x14 ([rsfec_top_rx_cfg]
    2. Disable FEC clock - Write 0x0000 to FEC register 0x04 ([rsfec_top_clk_cfg]
  2. Transceiver configuration:
    1. Write 0xCB to Transceiver channel register 0x4[7:0]
    2. Write 0x4C to Transceiver channel register 0x5[7:0]
    3. Write 0x0F to Transceiver channel register 0x6[7:0]
    4. Write 0xA6 to Transceiver channel register 0x7[7:0]
      Note: Repeat steps 2a to 2d for each Transceiver channel.
    5. Delay for 10,000 µs
    6. Write 0x00 to Transceiver channel register 0x200
    7. Write 0x00 to Transceiver channel register 0x201
    8. Write 0x00 to Transceiver channel register 0x202
    9. Write 0x81 to Transceiver channel register 0x203
    10. Wait for Transceiver channel register 0x207[7] is set to 1'b1
    11. Check that Transceiver channel register 0x207[0] is set 1'b0
    12. To enable PMA calibration when loading the new PMA settings, set bit 5 from Transceiver register 0x95
    13. To load initial PMA configuration, write 0x01 to Transceiver register 0x91
      Note: Repeat steps 2f to 2m for each Transceiver channel.
    14. Delay for 1000 µs
    15. To assert eio_sys_rst [Ethernet IO System Reset], write 0x0001 to MAC register 0x310
    16. Delay for 10,000 µs or use MAC signals to determine when it is ready
    17. To deassert eio_sys_rst [Ethernet IO System Reset], write 0x0000 to MAC register 0x310
    18. Delay for 1,000,000 µs or use MAC signals to determine when it is ready
  3. Rewrite MAC:
    1. Write 0x312C7 to MAC register 0x37a (Set Timer Window for Hi-BER Checks for CAUI-4 (4 x 25.78125 Gbps NRZ without FEC) configuration)
    2. Write 0x9FFD8028 to MAC register 0x40b (EHIP TX MAC Feature Configuration for CAUI-4 (4 x 25.78125 Gbps NRZ without FEC) configuration)
    3. Write 0x00000020 to MAC register 0x313 (Reset Sequencer RS-FEC disable)
    4. Set bits [3] and [9] of MAC register 0x30E (Use RX PCS Alignment)
    5. Delay for 10,000 µs
  4. Enable Internal Serial Loopback:
    1. Write 0x01 to Transceiver register 0x84
    2. Write 0x03 to Transceiver register 0x85
    3. Write 0x08 to Transceiver register 0x86
    4. Write 0x00 to Transceiver register 0x87
    5. Write 0x01 to Transceiver register 0x90
    6. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    7. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    8. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    Note: Repeat steps 4a to 4h for each Transceiver channel.
  5. Trigger PMA Adaptation:
    1. Write 0x18 to Transceiver register 0x84
    2. Write 0x01 to Transceiver register 0x85
    3. Write 0x2C to Transceiver register 0x86
    4. Write 0x00 to Transceiver register 0x87
    5. Write 0x01 to Transceiver register 0x90
    6. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    7. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    8. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    9. Write 0x00 to Transceiver register 0x84
    10. Write 0x00 to Transceiver register 0x85
    11. Write 0x6C to Transceiver register 0x86
    12. Write 0x00 to Transceiver register 0x87
    13. Write 0x01 to Transceiver register 0x90
    14. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    15. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    16. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    17. Write 0x01 to Transceiver register 0x84 (Enable Initial Adaptation)
    18. Write 0x00 to Transceiver register 0x85
    19. Write 0x0A to Transceiver register 0x86
    20. Write 0x00 to Transceiver register 0x87
    21. Write 0x01 to Transceiver register 0x90
    22. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    23. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    24. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
      Note: Repeat steps 5a to 5x for each Transceiver channel.
    25. Delay for 100 µs
    26. Write 0x00 to Transceiver register 0x84 (Check Initial Adaptation Status)
    27. Write 0x0B to Transceiver register 0x85
    28. Write 0x26 to Transceiver register 0x86
    29. Write 0x01 to Transceiver register 0x87
    30. Write 0x01 to Transceiver register 0x90
    31. Wait for Transceiver channel register 0x8A[7] until it becomes 1
    32. Wait for Transceiver channel register 0x8B[0] until it becomes 0
    33. Set 0x8A[7] to 1'b1 to clear 0x8A[7] value
    34. Wait for Transceiver register 0x88 lower 4 bits are set to 1'b0 (indicates end of adaptation)
      Note: Repeat steps 5z to 5ah for each Transceiver channel.
    35. Delay for 100000 µs

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