E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
Document Table of Contents

2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example

Figure 12. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example High Level Block Diagram
The E-tile Ethernet IP for Intel Agilex FPGA hardware design example includes the following components:
  • E-tile Ethernet IP for Intel Agilex FPGA core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
Result from c3_elane_pcsonly_traffic_basic_test.log file:
Info: Set JTAG Master Service Path


Info: Opened JTAG Master Service

	Test Start time is: 05:47:37
	Test Start date is: 03/21/2019


Info: Read all ELANE CSR registers

	Successfully Read  EHIPLANE Channel 0, User Register phy_revid                              , offset = 0x300, data = 0x11112015 
	Successfully Read  EHIPLANE Channel 0, User Register phy_scratch                           , offset = 0x301, data = 0x0 
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	Successfully Read  EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 

	C3 ELANE Channel 0 System Reset is successfully 


Info: Stopping the Channel 0 XGMII traffic generator

	Successfully Read  EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 
	Successfully Write EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 

Info: Starting the Channel 0 XGMII traffic generator

	Successfully Write EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x1 

Info: Comparing the Channel 0 XGMII traffic checker results

	Successfully Read  EHIPLANE Channel 0, XGMII Traffic GEN/CHK Register, offset = 0x2, data = 0x2 

Info: Channel 0, Iteration 1 is completed successfully
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Info: Channel 0, Iteration 5 is completed successfully


Info: Channel 0 test is completed 

	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 
	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x1 
	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x3 
	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x7 
	Successfully Read  EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x7 
	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x6 
	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x4 
	Successfully Write EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 
	Successfully Read  EHIPLANE Channel 1, User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 

	C3 ELANE Channel 1 System Reset is successfully 


Info: Stopping the Channel 1 XGMII traffic generator

	Successfully Read  EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 
	Successfully Write EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x0 

Info: Starting the Channel 1 XGMII traffic generator

	Successfully Write EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x0, data = 0x1 

Info: Comparing the Channel 1 XGMII traffic checker results

	Successfully Read  EHIPLANE Channel 1, XGMII Traffic GEN/CHK Register, offset = 0x2, data = 0x2 

Info: Channel 1, Iteration 1 is completed successfully
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Info: Channel 1, Iteration 5 is completed successfully


Info: Channel 1 test is completed 

	Successfully Read  RSFEC Register rsfec_top_rx_cfg                     , offset = 0x14, data = 0x11 
	Successfully Read  RSFEC Register arbiter_base_cfg                      , offset = 0x0, data = 0x1 
	Successfully Read  RSFEC Register rsfec_top_clk_cfg                    , offset = 0x4, data = 0x304 
	Successfully Read  RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x6611 
	Successfully Write RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x10001666 
	Successfully Read  RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x10001666 
	Successfully Write RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x6611 
	Successfully Read  RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x6611 

	Test End time is: 05:51:01
	Test End date is: 03/21/2019

Info: Closed JTAG Master Service



Info: Test <c3_elane_pcsonly_traffic_basic_test> Passed

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