E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.1.1. Directory Structure

The E-Tile Dynamic Reconfiguration Design Example file directories contain the following generated files for the design examples.

Figure 27. E-tile Dynamic Reconfiguration 10G/25G Ethernet and 25G Ethernet to CPRI Design Example Directory Structure
Figure 28. E-tile Dynamic Reconfiguration 24G CPRI Design Example Directory StructureThe example directory structure applies to all CPRI variants. <datarate> is either "24G" or "9P8G", depending on your IP core variation.
Figure 29. E-tile Dynamic Reconfiguration 100G Ethernet Design Example Directory Structure
Table 23.   E-Tile Dynamic Reconfiguration Design Example Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

<design_example_dir>/example_testbench/mentor/run_vsim.do

The Siemens* EDA ModelSim* SE or Questa* script to run the testbench.

<design_example_dir>/example_testbench/synopsys/run_vcs.sh

The Synopsys* VCS* script to run the testbench.

<design_example_dir>/example_testbench/synopsys/run_vcsmx.sh

The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

<design_example_dir>/example_testbench/run_xcelium.sh The Cadence* Xcelium* script to run the testbench.
Table 24.   E-Tile Dynamic Reconfiguration Design Example Hardware Design Example File Descriptions for 10G/25G Ethernet and CPRI Protocols

File Names

Description

<design_example_dir>/hardware_test_design/alt_ehipc3.qpf Intel® Quartus® Prime project file
<design_example_dir>/hardware_test_design/alt_ehipc3.qsf Intel® Quartus® Prime project settings file
<design_example_dir>/hardware_test_design/alt_ehipc3.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Agilex™ design.
<design_example_dir>/hardware_test_design/alt_ehipc3.sv Top-level Verilog HDL design example file
<design_example_dir>/hardware_test_design/common/ Hardware design example support files
Table 25.   E-Tile Dynamic Reconfiguration Design Example Hardware Design Example File Descriptions for 100G Ethernet Protocol

File Names

Description

<design_example_dir>/hardware_test_design/alt_ehipc3_hw.qpf Intel® Quartus® Prime project file
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.qsf Intel® Quartus® Prime project settings file
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Agilex™ design.
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.v Top-level Verilog HDL design example file
<design_example_dir>/hardware_test_design/common/ Hardware design example support files

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