E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
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4.4.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components

The 24G CPRI PHY hardware dynamic reconfiguration design example and 9.8G CPRI PHY hardware dynamic reconfiguration design example include the following components:
  • E-tile CPRI PHY Intel® FPGA IP core.
    • E-tile CPRI PHY Intel® FPGA IP core - 24G CPRI
    • E-tile CPRI PHY Intel® FPGA IP core - 9.8G CPRI PMA direct mode
  • XGMII packet generator and checker that coordinates the programming of the IP core and packet generation.
    Note: This component is only available for 24G CPRI variant.
  • 8B/10B pattern generator and checker that coordinates the programming of the IP core and packet generation.
  • Avalon® memory-mapped interface address decoder to decode reconfiguration address space for E-tile CPRI PHY Intel® FPGA IP core, transceiver, and RS-FEC modules during reconfiguration accesses.
  • Nios® II System that communicates with the Nios® II Software Build Tools (SBT) for Eclipse. You communicate with the client logic and E-tile Ethernet IP for Intel Agilex FPGA through the tool.
  • Native PHY in PMA Direct mode that acts as a channel PLL to provide EMIB clocks (for example, 402.8 MHz and 805.6 MHz), as required by the E-tile CPRI PHY Intel® FPGA IP core.
  • IOPLL to provide sampling clock (for example, 250 MHz for E-tile CPRI PHY Intel® FPGA IP core) and round-trip (RT) counter.
  • Sources and Probes module to measure the round-trip value of the E-tile CPRI PHY Intel® FPGA IP core in all supported speed modes.
The following sample outputs illustrate a successful hardware test run for a 24G CPRI PHY with RS-FEC IP core variation:
CPU is alive!


             Dynamic Reconfiguration Hardware Test

By default, the starting mode is CPRI24G_FEC.
      Please choose the Targeted mode available:
    1) CPRI24G
    2) CPRI12GFEC
    3) CPRI12G
    4) CPRI10GFEC
    5) CPRI10G
    6) CPRI9.8G
    7) CPRI6.0G
    8) CPRI4.9G
    9) CPRI3.0G
    a) CPRI2.4G
    9) Terminate test  -> If you terminate test halfway, you must reload the .sof file before retrigger the hardware test.

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