E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Document Table of Contents

4.2.5. 10GE/25GE Design Examples Registers

Table 30.   E-tile Ethernet IP for Intel Agilex FPGA Hardware Design Examples Register Map

Word Offset

Register Category

0x000000 – 0x000FFF Ethernet MAC and PCS registers
0x001000 – 0x001FFF Packet Generator and Checker registers
0x002000 – 0x002FFF PTP monitoring registers
0x010000 – 0x0107FF RS-FEC configuration registers
0x100000 – 0x1FFFFF Transceiver registers
Table 31.  Packet Client Registers You can customize the E-tile Ethernet IP for Intel Agilex FPGA hardware design example by programming the packet client registers.





HW Reset Value


0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. N/A RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string CLNT. N/A RO
0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit[29:11]: Reserved.
  • Bit[10:0]: These bits specify the transmit packet size in bytes.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. Set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Reserved
    • 01: Fixed mode
    • 10: Reserved
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, bit[1] of PKT_GEN_TX_CTRL register is used to turn off the packet generator.
  • Bit [7]
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits). 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits). 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits). 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits). 0x8765 RW
Note: In the 10G/25G Ethernet Design Example variant, the context CPRI PHY soft configuration register space does not refer to the CPRI PHY IP's register space.

Did you find the information on this page useful?

Characters remaining:

Feedback Message