E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.4.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. CPRI Protocol as DR Protocol.
  2. Under the CPRI Protocol tab:
    1. 24G CPRI RS-FEC as Select DR Design.
    2. Intel Agilex F-Series Transceiver-SoC Development Kit as the target development kit.
Figure 39. Simulation Block Diagram for 24G CPRI PHY with RS-FEC Dynamic Reconfiguration Design Example

The successful test displays the dynamic reconfiguration transition flow between various modes. Use preset HEX file provided for each design example or modify provided C code to enable specific transition simulation. For more information on HEX file, refer to Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench.

To test a specific transition, reorder the dynamic reconfiguration transition flow tests in the main.c file and regenerate a new HEX file. Each test describes a transition from the starting rate to the destination rate.

This is the default simulation test sequence based on the provided HEX file.

  1. Toggle sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Dynamic reconfiguration (DR) test from 24G CPRI with RS-FEC to 12G CPRI with RS-FEC
  3. DR test from 12G CPRI with RS-FEC to 10G CPRI with RS-FEC
  4. DR test from 10G CPRI with RS-FEC to 9.8G CPRI
  5. DR test from 9.8G CPRI to 6G CPRI
  6. DR test from 6G CPRI to 4.9G CPRI
  7. DR test from 4.9G CPRI to 3G CPRI
  8. DR test from 3G CPRI to 2.4G CPRI
  9. DR test from 2.4G CPRI to 24G CPRI with RS-FEC
Each of the dynamic reconfiguration tests follows these steps:
  1. Assert sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Disable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  3. Perform reference clock mux switching. Use this step when reconfiguring from a high-speed mode (10G/ 12G/24G) to a PMA direct low-speed mode (2.4G/3G/4.9G/6G/9.8G) and vice versa. For more information about the details of the changed register values, refer to the c3_reconfig.c file.
    1. Switch the PMA controller clock to the transceiver refclk1 clock.
    2. Change refclk reference clock from 184.32 MHz (i_clk_ref[0]) to 153.6 MHz (i_clk_ref[1]).
    3. Switch the PMA controller clock to the transceiver refclk0 clock.
    Note: Steps 3a and 3c are only applicable for Ethernet dynamic reconfiguration hardware tests to avoid potential hardware glitch due to the reference clock switch operation. These steps are available in the hardware test code but skip in the simulation test code.
  4. Trigger PMA analog reset. For more information about register descriptions, refer to the E-tile Transceiver PHY User Guide.
  5. Reconfigure the following registers for the Ethernet, RS-FEC, and transceiver blocks. For more information about the details of the changed register values, refer to the c3_reconfig.c file. For more information about the register descriptions, refer to the E-tile Hard IP for Ethernet and CPRI PHY Intel® FPGA IPs User Guide.
  6. Adjust the phase offset of a recovered clock. Use PMA attribute code 0x000E in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  7. Enable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  8. Enable internal serial loopback. Use PMA attribute code 0x0008 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  9. Deassert sl_tx_rst_n and sl_rx_rst_n reset signals.
  10. Wait for PIO_OUT[3:0] = 0x7 (o_sl_rx_pcs_ready, o_sl_rx_block_lock, and o_ehip_ready asserted).
  11. Clear Ethernet statistic counters.
  12. Enable the packet generator to start sending packets of data.
  13. Check for checker_pass status and waiting for PIO_OUT[3:0] = 0xF (checker_pass, o_sl_rx_pcs_ready, o_sl_rx_block_lock, and o_ehip_ready asserted).
  14. Disable the packet generator to stop sending packets.
The following sample output illustrates a successful simulation test run for a 24G MAC+PCS with RS-FEC IP core variation.
# CPU is alive!
# End of test
# Nios has completed its transactions          1995670000
# Simulation PASSED          1995670000
# ** Note: $finish    : ./../basic_avl_tb_top.sv(634)
#    Time: 1995670 ns  Iteration: 1  Instance: /basic_avl_tb_top

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