E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
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2.3.1.2. E-tile Ethernet IP for Intel Agilex FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. Under the IP tab:
    1. 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
    2. 100GE Channel as Active channel(s) at startup.
    3. Enable IEEE 1588 PTP.
    4. Enable RSFEC to use the RS-FEC feature.
  2. Under the 100GE tab:
    1. 100G as the Ethernet rate.
    2. MAC+1588PTP+PCS+(528,514)RSFEC as the Ethernet IP layer.
Figure 14. Simulation Block Diagram for E-tile Ethernet IP for Intel Agilex FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Design Example

In this design example, the testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.

To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The standard specifies an alignment marker interval of 16,384 words in each virtual lane. The simulation model with the testbench implements an alignment marker interval of 512 words.

The successful test run displays output confirming the following behavior:

  1. Waiting for PLL to lock.
  2. Waiting for RX transceiver reset to complete.
  3. Waiting for RX alignment.
  4. Sending 10 packets.
  5. Receiving those packets.
  6. Displaying Testbench complete.

The following sample output illustrates a successful simulation test run for a 100GE, MAC+PCS, RS-FEC, PTP IP core variation.

# o_tx_lanes_stable is 1 at time             346295000
# waiting for tx_dll_lock....
# TX DLL LOCK is 1 at time             405180363
# waiting for tx_transfer_ready....
# TX transfer ready is 1 at time             405500235
# waiting for rx_transfer_ready....
# RX transfer ready is 1 at time             416575803
# EHIP PLD Ready out is 1 at time             416632000
# EHIP reset out is 0 at time             416768000
# EHIP reset ack is 0 at time             416844540
# EHIP TX reset out is 0 at time             417184000
# EHIP TX reset ack is 0 at time             468265476
# waiting for EHIP Ready....
# EHIP READY is 1 at time             468389597
# EHIP RX reset out is 0 at time             470288000
# waiting for rx reset ack....
# EHIP RX reset ack is 0 at time             470301064
# Waiting for RX Block Lock
# EHIP RX Block Lock  is high at time             511027716
# Waiting for AM lock
# EHIP RX AM Lock  is high at time             511027716
# Waiting for RX alignment
# RX deskew locked
# RX lane aligmnent locked
# Configure TX extra latency
# ====> writedata = 0004267a 
# 
# Configure RX extra latency
# ====> writedata = 8003af52 
# 
# Waiting for TX PTP Ready
# TX PTP ready
# Waiting for RSFEC alignment locked
# Reading rsfec_ln_mapping_rx_0
# rsfec_ln_mapping_rx_0 = 32'h0
.
.
.
# Reading rsfec_cw_pos_rx_3
# rsfec_cw_pos_rx_3 = 32'h7dd
# min skew value = 32'h1
# lane_skew_adjust = 32'h1
# Tlat_final = 32'h4
# Generate VL offset data
# before-rotation: VL[PL] 0[0], deskew_delay = 4 UI, vl_offset_bits = 4
# After rotation: VL_OFFSET for RVL[PL] 4[0] = 0 ns 27b8 Fns, Sign bit= 0 
.
.
.
# before-rotation: VL[PL] 19[0], deskew_delay = 4 UI, vl_offset_bits = 8
# before-rotation: VL[PL] 19[0], deskew_delay = 4 UI, vl_offset_bits_shifted = -322
# After rotation: VL_OFFSET for RVL[PL] 3[0] = c ns 7d5d Fns, Sign bit= 1 
# Writing VL offset data for VL 0
# ====> writedata = 00000004 
# 
# ====> writedata = 000027b8 
.
.
.
# Writing VL offset data for VL 19
# ====> writedata = 00000003 
# 
# ====> writedata = 800c7d5d 
# 
# Waiting for RX PTP Ready
# RX PTP ready
# ** Sending Packet           1...
# ** Sending Packet           2...
# ** Sending Packet           3...
# ** Sending Packet           4...
# ** Sending Packet           5...
# ** Sending Packet           6...
# ** Sending Packet           7...
# ** Sending Packet           8...
# ** Sending Packet           9...
# ** Received Packet          1...
# ** Sending Packet          10...
# ** Received Packet          2...
# ** Received Packet          3...
# ** Received Packet          4...
# ** Received Packet          5...
# ** Received Packet          6...
# ** Received Packet          7...
# ** Received Packet          8...
# ** Received Packet          9...
# ** Received Packet         10...
# **
# ** Testbench complete.
# **
# *****************************************
# ** Note: $finish    : ./basic_avl_tb_top.sv(674)
#    Time: 530600 ns  Iteration: 0  Instance: /basic_avl_tb_top

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