E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
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4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components

The 10GE/25GE hardware dynamic reconfiguration design example includes the following components:
  • E-tile Ethernet IP for Intel Agilex FPGA core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • Avalon® -MM address decoder to decode reconfiguration address space for MAC, transceiver, and RS-FEC modules during reconfiguration accesses.
  • Nios® II System that communicates with the Nios® II Software Build Tools (SBT) for Eclipse. You communicate with the client logic and E-tile Ethernet IP for Intel Agilex FPGA through the tool.
  • Native PHY in PMA Direct mode that acts as a channel PLL to provide EMIB clocks (for example, 402.8 MHz and 805.6 MHz), as required by the E-tile Ethernet IP for Intel Agilex FPGA core.
  • IO PLL to provide datapath clocks 62.5 MHz and 125 MHz as required by the Triple-Speed Ethernet Intel FPGA IP.
  • ToD master module to provide a continuous flow of current time-of-day information to Triple-Speed Ethernet Intel FPGA IP.
The following sample outputs illustrate a successful hardware test run for a 25GE, MAC+PCS, RS-FEC IP core variation:
CPU is alive!


             Dynamic Reconfiguration Hardware Test

By default, the starting mode is 25G_FEC.
      Please choose one of Dynamic reconfiguration:
    0) 25G_FEC   -> 25G_noFEC -> 10G -> 25G_noFEC -> 25G_FEC -> 10G -> 25G_FEC
    1) 25G_FEC   -> 25G_noFEC
    2) 25G_noFEC -> 25G_FEC
    3) 25G_FEC   -> 10G
    4) 10G       -> 25G_FEC
    5) 25G_noFEC -> 10G
    6) 10G       -> 25G_noFEC
    9) Terminate test
       If you terminate test halfway, you must reload the .sof file before retrigger the hardware test.

Enter a Valid Selection (0,1,3,9):

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