E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
Public
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4.1.5.1. Running the Design Example in Hardware

If you select Intel Agilex F-Series Transceiver-SoC Development Kit option as the Target Development Kit in the E-Tile Dynamic Reconfiguration Design Example parameter editor in Intel® Quartus® Prime Pro Edition software, refer to Power Management Setting for Agilex Transceiver Signal Integrity Development Kit on how to configure the power management setting that can be included in the Quartus Setting File (.qsf) for the Intel Agilex F-Series Transceiver-SoC Development Kit.

Follow the steps below to run the design example in hardware:

  1. In the Intel® Quartus® Prime Pro Edition software, compile the design example with the power management setting included to obtain a working SRAM Object File (.sof) file.
  2. Download the .sof file to the Intel Agilex F-Series Transceiver-SoC Development Kit .
  3. Launch the Clock Control application and set new frequencies for the design example. Below is the frequency setting in the Clock Control application. Select Si5341A(U3) to program:
    • U34, OUT0 = 156.25 MHz
    • U36, OUT1 = 100 MHz
    • U37, OUT2 = 153.6 MHz for the CPRI designs that target 24.3 Gbps CPRI with RS-FEC line rates.

    This step is only applicable for CPRI protocol and Ethernet to CPRI protocol related dynamic reconfiguration design examples.

  4. In the Intel® Quartus® Prime Pro Edition software, select Tools > Nios II Software Build Tools for Eclipse.
  5. Create a new workspace when the Workspace Launcher window prompt appears. Click OK to open the workspace.
  6. In the Nios II - Eclipse window, select File > New > Nios II Application and BSP from Template. A Nios II Application and BSP from Template appears.
  7. In the Nios II Application and BSP from Template window, fill in the following information:
    • For SOPC Information File name, browse to <design_example_dir>/hardware_test_design/nios_system and open the SOPC Information File (nios_system.sopcinfo) for your design. Click OK to select the file and Eclipse automatically loads all CPU settings.
    • For Project name, specify your desired project name. This example uses dynamic_reconfiguration_hardware.
  8. Click Finish to generate the project. The Intel® Quartus® Prime Pro Edition software creates a new directory named software in the specified project location.
  9. Replace the C-code source files located in your new software directory ( <design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_hardware) with the following C-code source files from the <design_example_dir>/software/dynamic_reconfiguration_hardware design:
    • c3_reconfig.c
    • c3_reconfig.h
    • c3_function.c
    • flow.c
    • main.c
    • packet_gen.c
    • packet_gen.h
      Note: The packet_gen.c and packet_gen.h files are only applicable for Ethernet dynamic reconfiguration (DR) design example and Ethernet to CPRI DR design example variants.
  10. In the Nios II - Eclipse window, press F5 or right-click your project and select Refresh to refresh the window and reload the new files into the project.
  11. On the Project Explorer view, right-click dynamic_reconfiguration_hardware and select Build Project. Ensure the dynamic_reconfiguration_hardware.elf file is generated in the new <design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_hardware directory.
  12. To run the hardware test, right-click dynamic_reconfiguration_hardware in the Project Explorer view, point to Run As and select Nios II Hardware.
    If the Run Configurations dialog box appears, verify that Project name and ELF file name contain relevant data, then click Run.
In the Interactive GUI dialog box, select the dynamic reconfiguration hardware test.
Note: The GUI dialog box varies based on the selected dynamic reconfiguration hardware test variant.

The following is a hardware test example for the 25G Ethernet with PTP and RS-FEC variant.

CPU is alive!


             Dynamic Reconfiguration Hardware Test

By default, the starting mode is 25G_PTP_FEC.
      Please choose one of Dynamic reconfiguration:
    0) 25G_PTP_FEC    -> 25G_PTP_noFEC -> 10G_PTP -> 25G_PTP_noFEC -> 25G_PTP_FEC -> 10G_PTP -> 25G_PTP_FEC
    1) 25G_PTP_FEC    -> 25G_PTP_noFEC
    2) 25G_PTP_noFEC  -> 25G_PTP_FEC
    3) 25G_PTP_FEC    -> 10G_PTP
    4) 10G_PTP        -> 25G_PTP_FEC
    5) 25G_PTP_noFEC  -> 10G_PTP
    6) 10G_PTP        -> 25G_PTP_noFEC
    9) Terminate test
       If you terminate test halfway, you must reload the .sof file before retrigger the hardware test.

Enter a Valid Selection (0,1,3,9):

The following is a hardware test example for CPRI variants.

CPU is alive!


             Dynamic Reconfiguration Hardware Test

By default, the starting mode is CPRI24G_FEC.
      Please choose the Targeted mode available:
    1) CPRI24G
    2) CPRI12GFEC
    3) CPRI12G
    4) CPRI10GFEC
    5) CPRI10G
    6) CPRI9.8G
    7) CPRI6.0G
    8) CPRI4.9G
    9) CPRI3.0G
    a) CPRI2.4G
    9) Terminate test  -> If you terminate test halfway, you must reload the .sof file before retrigger the hardware test.

Enter a Valid Selection:

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