E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public
Document Table of Contents

2.5. Document Revision History for the E-tile Hard IP for Ethernet Intel® Agilex™ FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.12.11 21.3 20.2.0
  • Added support for Questa simulator.
  • Removed support for NCSim simulator.
2021.08.04 21.2 20.2.0
  • Updated steps in the following section:
    • Generating the Design
    • Compiling and Configuring the Design Example in Hardware
  • Added new command setting: EnhancedPTPAccuracy.
  • Updated the design example support in Table: Supported Design Example Variants for 10GE/25GE.
  • Added a new signal for SyncE feature in Figure: 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware DesignExample High Level Block Diagram and Table: 10GE/25GE Hardware Design Example Interface Signals.
2021.01.27 20.3 20.1.1 Added new topic: Ethernet Toolkit
2020.06.29 20.2 20.1.0 Revised Y1 description in the Compiling and Configuring the Design Example in Hardware section.
2019.12.30 19.4 19.4.0
  • Updated Table: List of Supported Design Example Variants to include hardware design example support.
  • Added hardware design example support for 10GE/25GE with optional RS-FEC design example.
  • Added hardware design example support for 100GE with optional RS-FEC design example.
  • Updated description of PMA adaptation setting in the Generating the Design section.
  • Added Asynchronous clock support for the 100GE MAC+PCS with (528,514) RS-FEC and PTP variant.
  • Restructured topics to improve the content flow.
2019.10.18 19.3 19.3.0 Initial Release.

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