E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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Document Table of Contents

2.1.2. Generating the Design

Procedure
Example Design Tab in the E-tile Ethernet IP for Intel Agilex FPGA Parameter Editor
Follow these steps to generate the E-tile Ethernet IP for Intel Agilex FPGA testbench:
  1. In the IP Catalog, locate and select E-tile Ethernet IP for Intel Agilex FPGA . The New IP Variation window appears.
  2. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  3. Click OK. The parameter editor appears.
  4. On the IP, 100GE, or 10GE/25GE tabs, specify the parameters for your IP core variation.
  5. Change PMA adaptation setting. To change the PMA adaptation setting for the optimal performance, go to PMA Adaptation tab. This step is optional.
    1. Select a PMA adaptation preset for PMA adaptation Select parameter.
    2. Click PMA Adaptation Preload to load the initial and continuous adaptation parameters.
    3. Specify the number of PMA configurations to support when multiple PMA configurations are enabled using Number of PMA configuration parameter.
    4. Select which PMA configuration to load or store using Select a PMA configuration to load or store.
    5. Click Load adaptation from selected PMA configuration to load the selected PMA configuration settings.

    For more information about the PMA adaptation parameters, refer to the E-Tile Transceiver PHY User Guide.

    Note: If you require more information about the PMA adaptation parameters, contact My Intel support.
  6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  7. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL. If you select VHDL, you must simulate the testbench with a mixed-language simulator. The device under test in the ex_<datarate> directory is a VHDL model, but the main testbench file is a System Verilog file.
  8. Under Target Development Kit, select the Agilex F-series Transceiver-SoC Development Kit - AGFB014R24A2E2V, Agilex F-series Transceiver-SoC Development Kit - AGFB014R24A2E2VR0 or select None. If you select a specific Development Kit as the Target Development Kit, the design example is generated based on a specific device and it overwrites the device you selected in your project file. If you select None as the Target Development Kit, ensure the selected device is your targeted device and adjust the pins assignment in the .qsf file. By default, .qsf file is generated based on the device used in the development kit
  9. Click the Generate Example Design button. The Select Example Design Directory window appears.
  10. If you want to modify the design example directory path or name from the defaults displayed (alt_ehipc3_ fm_ 0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).

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