E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 12/11/2021
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4.3.4. 25G Ethernet to CPRI Design Example Interface Signals

The following signals are hardware dynamic reconfiguration design example signals for 25G Ethernet to CPRI variants.

Table 34.  25G Ethernet to CPRI Dynamic Reconfiguration Design Example Hardware Interface Signals
Signal Direction Comments
clk100 Input Input clock for reconfiguration. Drive at 100 MHz. The intent is to drive this from a 100 MHz oscillator on the board.
cpu_resetn Input Input reset for Nios® II System.
ref_clk156MHz Input 156.25 MHz input clock for the 25G Ethernet IP core. Connect to i_clk_ref[0] in 25G Ethernet IP core.
ref_clk184MHz Input 184.32 MHz input clock for the 10G/24G CPRI mode. Connect to the i_clk_ref[1] in 25G Ethernet IP core.
ref_clk153MHz Input 153.6 MHz input clock for the 2.4G/4.9G/9.8G CPRI mode. Connect to the i_clk_ref[2] in 25G Ethernet IP core.
tx_serial_data/_n Output Transmit serial data for channel PLL (PMA direct mode).
rx_serial_data/_n Input Receiver serial data for channel PLL (PMA direct mode).
o_tx_serial Output Transmit serial data.
i_rx_serial Input Receiver serial data.

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