E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.3.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC

This section provides a sequential flow for dynamic reconfiguration of 25GbE PTP FEC configuration to 24G CPRI FEC configuration. For other variations, you can refer to the generated C file that provides comprehensive information through comments.
  1. Assert the i_sl_tx_rst_n and i_sl_rx_rst_n reset signals.
  2. Disable Serdes (via PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
  3. Perform switching of reference clock mux:
    1. Switch PMA controller clock to XCVR_Refclk1.
    2. Refclk switching from i_clk_ref[0] (156.25MHz) to i_clk_ref [1] (184.32MHz).
    3. Switch PMA controller clock to XCVR_Refclk0.
    Note: Steps a and c are required for hardware test only to avoid potential hardware glitch due to reference clock switch operation. You can skip these steps in simulation.
    For more information, refer to the E-Tile Transceiver PHY User Guide.
  4. Perform PMA Analog Reset. For more information, refer to the E-Tile Transceiver PHY User Guide.
  5. Change the following registers:
    Table 38.  Registers: 25GbE PTP FEC to 24G CPRI FEC
    Block Configuration Registers Offset From Value To Value
    ELANE txmac_ehip_cfg 0x40B 0x027E00E0 0x027E01E0 (simulation)

    0x9FFE01E0 (hardware)

    phy_ehip_pcs_modes 0x30E 0x00000093 0x0000_0083
    phy_ehip_mode_muxes 0x30D 0x00000000 0x00000008
    tx_data_path_mux 0x350 0x003F1001 0x003F1002
    rx_data_path_mux 0x255 0x00000001 0x00000002
    RS-FEC rsfec_top_clk_cfg

    fec_lane_ena [3:0]

    0x4C 0x00000000 0x00000003
    Transceiver TX Refclk Ratio 0x84 0xA5 0x84
    0x85 0 0
    0x86 0x5 0x5
    0x87 0 0
    RX Refclk Ratio 0x84 0xA5 0x84
    0x85 0 0
    0x86 0x6 0x6
    0x87 0 0
  6. Adjust the phase offset of a recovered clock using the RX Phase Slip (via PMA attribute code 0x000E). For more information, refer to the E-Tile Transceiver PHY User Guide.
  7. Enable Serdes (via PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
  8. Enable internal serial loopback (via PMA attribute code 0x0008). For more information, refer to the E-Tile Transceiver PHY User Guide.
  9. Deassert the i_sl_tx_rst_n and i_sl_rx_rst_n reset signals.
  10. Wait until:
    PIO_OUT[3:0] = 0xF (o_tx_ptp_ready, o_sl_rx_pcs_ready, o_sl_rx_block_lock, o_ehip_ready asserted)
  11. Send packets for RX CDR deskew training, wait until:
    PIO_OUT[4] = 0x1 (o_rx_ptp_raedy asserted)
  12. Clear ELANE statistic counters.
  13. Enable packet generator to send 20 packets data.
  14. Check TX packet count statistic counter to ensure all the packets are sent, then stop packet generator.
  15. Check for the expected packets to be received by packet checker.

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