E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. Ethernet Protocol as DR Protocol.
  2. Under the 10G/25G Ethernet Protocol tab:
    1. 25G RS-FEC as Select DR Design.
    2. Other Development Kits as the target development kit.
Figure 33. Simulation Block Diagram for E-Tile Ethernet IP for Intel® Agilex™ FPGA 10GE/25GE with RS-FEC Dynamic Reconfiguration Design Example

The successful test displays the dynamic reconfiguration transition flow between various modes. Use preset HEX file provided for each design example or modify provided C code to enable specific transition simulation. For more information on HEX file, refer to Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench.

To test a specific transition, reorder the dynamic reconfiguration transition flow tests in the main.c file and regenerate a new HEX file. Each test describes a transition from the starting rate to the destination rate.

This is the default simulation test sequence based on the provided HEX file.

  1. Toggle sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Link Initialization. For more information, refer to Performing the Link Initialization.
  3. Dynamic reconfiguration (DR) test from 25G PTP with RS-FEC to 25G PTP without RS-FEC
  4. DR test from 25G PTP without RS-FEC to 10G PTP
  5. DR test from 10G PTP to 25G PTP without RS-FEC
  6. DR test from 25G PTP without RS-FEC to 25G PTP with RS-FEC
  7. DR test from 25G PTP with RS-FEC to 10G PTP
  8. DR test from 10G PTP to 25G PTP with RS-FEC
Each of the dynamic reconfiguration tests follows these steps:
  1. Assert sl_tx_rst_n and sl_rx_rst_n reset signals.
  2. Disable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  3. Trigger PMA analog reset. For more information about register descriptions, refer to the E-tile Transceiver PHY User Guide.
  4. Change transceiver TX bit/refclk ratio to the destination rate. The refclk is 156.25 MHz.
  5. Change transceiver RX bit/refclk ratio to the destination rate. The refclk is 156.25 MHz.
  6. Reconfigure the following registers for the Ethernet, RS-FEC, and transceiver blocks. For more information about the details of the changed register values, refer to the c3_reconfig.c file. For more information about the register descriptions, refer to the E-tile Hard IP for Ethernet and CPRI PHY Intel® FPGA IPs User Guide.
  7. Adjust the phase offset of a recovered clock. Use PMA attribute code 0x000E in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  8. Enable SERDES. Use PMA attribute code 0x0001 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  9. Enable internal serial loopback. Use PMA attribute code 0x0008 in the E-tile Transceiver PHY User Guide: PMA Attribute Codes section.
  10. Deassert sl_tx_rst_n and sl_rx_rst_n reset signals.
  11. Wait for PIO_OUT[4:0] = 0x1F (o_sl_rx_ptp_ready, o_sl_rx_pcs_ready, o_sl_rx_block_lock, and o_ehip_ready asserted).
  12. Clear Ethernet statistic counters.
  13. Enable the packet generator to start sending packets of data.
  14. Check for checker_pass status and waiting for PIO_OUT[3:0] = 0xF (checker_pass, o_sl_rx_pcs_ready, o_sl_rx_block_lock, and o_ehip_ready asserted).
The following sample output illustrates a successful simulation test run for a 25GE MAC+PCS with RS-FEC IP core variation.
# CPU is alive!
# INFO:  PKT_RX_CNT received = 10
# INFO:  PKT_RX_CNT received = 20
# INFO:  PKT_RX_CNT received = 30
# INFO:  PKT_RX_CNT received = 40
# INFO:  PKT_RX_CNT received = 50
# INFO:  PKT_RX_CNT received = 60
# INFO:  PKT_RX_CNT received = 70
# End of test
# Nios has completed its transactions          4535480000
# Simulation PASSED          4535480000
# ** Note: $finish    : ./../basic_avl_tb_top.sv(522)
#    Time: 4535480 ns  Iteration: 1  Instance: /basic_avl_tb_top

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