E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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2.2. 10GE/25GE with Optional RS-FEC Design Examples

The 10GE/25GE design example demonstrates an Ethernet solution for Intel® Agilex™ devices using the E-tile Ethernet IP for Intel Agilex FPGA core with the following variants:

Table 5.  Supported Design Example Variants for 10GE/25GEAll variant supports up to 4 channels.
Variant Intel® Agilex™ Design Example Support
MAC+PCS with Optional RS-FEC 3 Simulation and compilation-only project, and hardware design example
MAC+PCS with Optional RS-FEC and PTP3 Simulation and compilation-only project, and hardware design example
PCS Only with Optional RS-FEC3 Simulation and compilation-only project, and hardware design example
OTN with Optional RS-FEC3 Simulation and compilation-only project
FlexE with Optional RS-FEC3 Simulation and compilation-only project
Custom PCS with Optional RS-FEC3 Simulation and compilation-only project, and hardware design example
3 RS-FEC is not supported in 10GE variant.

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