E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public
Document Table of Contents

2.2.4. 10GE/25GE Design Examples Registers

Table 7.   E-tile Ethernet IP for Intel Agilex FPGA Hardware Design Examples Register MapLists the memory mapped register ranges for all 10GE/25GE hardware design example variants. You access these registers with the reg_read and reg_write functions in the System Console.
Channel Number Word Offset Register Type
0 0x000000 KR4 registers
0x000300 RX PCS registers
0x000400 TX MAC registers
0x000500 RX MAC registers
0x000800 TX Statistics Counter registers
0x000900 RX Statistics Counter registers
0x001000 Packet Client and Packet Generator registers
0x002000 PTP monitoring registers
0x010000 RS-FEC configuration registers
0x100000 Transceiver registers
1 0x200000 KR4 registers
0x200300 RX PCS registers
0x200400 TX MAC registers
0x200500 RX MAC registers
0x200800 TX Statistics Counter registers
0x200900 RX Statistics Counter registers
0x201000 Packet Client registers
0x202000 PTP monitoring registers
0x210000 RS-FEC configuration registers
0x300000 Transceiver registers
2 0x400000 KR4 registers
0x400300 RX PCS registers
0x400400 TX MAC registers
0x400500 RX MAC registers
0x400800 TX Statistics Counter registers
0x400900 RX Statistics Counter registers
0x401000 Packet Client registers
0x402000 PTP monitoring registers
0x410000 RS-FEC configuration registers
0x500000 Transceiver registers
3 0x600000 KR4 registers
0x600300 RX PCS registers
0x600400 TX MAC registers
0x600500 RX MAC registers
0x600800 TX Statistics Counter registers
0x600900 RX Statistics Counter registers
0x601000 Packet Client registers
0x602000 PTP monitoring registers
0x610000 RS-FEC configuration registers
0x700000 Transceiver registers
Table 8.  Packet Client Registers You can customize the E-tile Ethernet IP for Intel Agilex FPGA hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string "CLNT" RO
0x1008 Packet Size Configure [29:0] Specifies the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit [29:16]: Specify the upper limit of the packet size in bytes. This is only applicable to incremental mode.
  • Bit [13:0]:
    • For fixed mode, these bits specify the transmit packet size in bytes.
    • For incremental mode, these bits specify the incremental bytes for a packet.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specifies the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. Set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Random mode
    • 01: Fixed mode
    • 10: Incremental mode
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, bit [1] of PKT_GEN_TX_CTRL register is used to turn off the packet generator.
  • Bit [7]:
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits) 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits) 0x1234 RW
0x1013 Source address lower 32bits [31:0] Source address (lower 32 bits) 0x43210ADD RW
0x1014 Source address upper 16bits [15:0] Source address (upper 16 bits) 0x8765 RW
0x1016 PKT_CL_LOOPBACK_RESET [0] MAC loopback reset. Set to the value of 1 to reset the design example MAC loopback. 1'b0 RW
Table 9.  MII Packet Generator Registers

Addr

Name

Bit

Description

HW Reset Value

Access

0x0 XGMII_PKTGEN_START [0] Start or stop packet generator for MII interface. Valid for custom PCS, OTN, FlexE, and PCS_only modes.
  • 1’b0: Stop
  • 1’b1: Start
0 RW
0x2 XGMII_PKTGEN_PASS [1] Checks for pass or fail status of MII interface packet generation.
  • 1’b0: Fail
  • 1’b1: Pass
0 RO

Did you find the information on this page useful?

Characters remaining:

Feedback Message