E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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3.1.3. Directory Structure

The E-tile CPRI PHY IP core design example file directories contain the following generated files for the design example.
Figure 22. Directory Structure of the Generated Example Design<datarate> is either "2_4", "3", "4_9", "6", "9_8", "10", "12" or "24", depending on your IP core variation.
Table 17.   E-tile CPRI PHY Intel® FPGA IP Core Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/alt_cpriphy_c3_top.sv DUT wrapper that instantiates DUT and other testbench components.

Testbench Scripts

<design_example_dir>/example_testbench/run_vsim.do The Siemens* EDA ModelSim* SE or Questa* script to run the testbench.

<design_example_dir>/example_testbench/run_vcs.sh

The Synopsys* VCS* script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.
<design_example_dir>/example_testbench/run_xcelium.sh The Xcelium* script to run the testbench.
Table 18.   E-tile CPRI PHY Intel® FPGA IP Core Hardware Design Example File Descriptions
File Names Descriptions
<design_example_dir>/hardware_test_design/alt_cpriphy_c3_hw.qpf Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/alt_cpriphy_c3_hw.qsf Intel® Quartus® Prime project setting file.
<design_example_dir>/hardware_test_design/alt_cpriphy_c3_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Agilex™ design.
<design_example_dir>/hardware_test_design/alt_cpriphy_c3_hw.v Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/alt_cpriphy_c3_top.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/hardware_test_design/hwtest_sl/main_script.tcl Main file for accessing System Console.

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