E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.5. 25G Ethernet to CPRI Design Examples Registers

Table 35.   E-Tile Hard IP for Ethernet to CPRI Intel® FPGA IP Hardware Design Examples Register Map

Word Offset

Register Category

0x000000 – 0x000FFF Ethernet MAC and PCS registers
0x001000 – 0x001FFF Packet Generator and Checker registers
0x002000 – 0x002FFF PTP monitoring registers
0x010000 – 0x0107FF RS-FEC configuration registers
0x100000 – 0x1FFFFF Transceiver registers
0x003000 – 0x003FFF CPRI PHY soft registers
Table 36.  Packet Client Registers You can customize the E-Tile Hard IP for Ethernet to CPRI Intel® FPGA IP hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. N/A RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string CLNT. N/A RO
0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit[29:11]: Reserved.
  • Bit[10:0]: These bits specify the transmit packet size in bytes.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. Set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Reserved
    • 01: Fixed mode
    • 10: Reserved
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, bit[1] of PKT_GEN_TX_CTRL register is used to turn off the packet generator.
  • Bit [7]
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits). 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits). 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits). 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits). 0x8765 RW
Table 37.   CPRI PHY Soft Registers You can view the status ports and TX and RX datapath latencies of the CPRI PHY soft module by accessing the CPRI PHY registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x3000 rx_bitslip boundary_ sel [9:5] Indicates the number of bits that the 8B/10B RX PCS block slipped to achieve a deterministic latency. 0x0 RO
cpri_fec_en [4] Used by deterministic latency, this bit indicates whether the RS-FEC block is enabled.
  • [0]: Not enabled
  • [1]: Disabled
0x1 RW
cpri_rate_ sel [3:0] Used by EFIFO and deterministic latency, this bit indicates the CPRI PHY speed selection.
Bit [3:0]:
  • 0 ~ 1: Reserved
  • 2: 2.4G
  • 3: 3G
  • 4: 4.9G
  • 5: 6G
  • 6: 9.8G
  • 7 ~ 8: Reserved
  • 9: 10G
  • 10: 12G
  • 11: 24G
  • 12 ~ 15: Reserved
Note: The TX/RX datapath must be reconfigured after every setting change.
0xB RW
0x3001 dl_reset [1]

Deterministic Latency (DL) soft reset

Provides a soft reset to the DL block.
  • 0: DL block is not under reset.
  • 1: DL block is being reset.
Note: This is not a self-clearing reset.
0x0 RW
measure_ valid [0] Indicates whether the deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
0x0 RO
0x3002 tx_delay [20:0]

TX Datapath Latency

Displays the TX datapath deterministic latency measurement values measured in sampling_clk cycles.

measure_valid must be set prior taking the measurement.

0x0 RO
0x3003 rx_delay [20:0]

RX Datapath Latency

Displays the RX datapath deterministic latency measurement values measured in sampling_clk cycles.

measure_valid must be set prior taking the measurement.

0x0 RO

Did you find the information on this page useful?

Characters remaining:

Feedback Message