E-tile Hard IP Intel® Agilex™ Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 12/11/2021
Public

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4.1.2.1. Design Example Parameters

The E-Tile Dynamic Reconfiguration Design Example parameter editor allows you to specify certain parameters before generating the design example.
Table 26.  Parameters in the E-Tile Dynamic Reconfiguration Design Example Parameter Editor
Parameter Options Description
Select DR Protocol
  • 10G/25G Ethernet Protocol
  • CPRI Protocol
  • 25G Ethernet to CPRI Protocol
  • 100G Ethernet
Available protocols for dynamic reconfiguration design example generation.
Parameter Settings: 10G/25G Ethernet Protocol (This tab is only applicable when you select 10G/25G Ethernet Protocol)
Select DR Design
  • 25G 1588 PTP RS-FEC
  • 25G RS-FEC
Available base variants for Ethernet Dynamic Reconfiguration design example generation.
Parameter Settings: CPRI Protocol (This tab is only applicable when you select CPRI Protocol)
Select DR Design
  • 24G CPRI RS-FEC
  • 9.8G CPRI
Available base variant for CPRI Dynamic Reconfiguration design example generation.
Parameter Settings: 25G Ethernet to CPRI Protocol (This tab is only applicable when you select 25G Ethernet to CPRI Protocol)
Select DR Design 25GE PTP RS-FEC Available base variant for Ethernet to CPRI Dynamic Reconfiguration design example generation.
Parameter Settings: 100G Ethernet Protocol (This tab is only applicable when you select 100G Ethernet Protocol)
Select DR Design 100G Ethernet MAC+PCS RS-FEC Available base variants for 100G Ethernet Dynamic Reconfiguration design example generation.
Select DR Controller Location
  • Internal
  • External
Internal Dynamic Reconfiguration selection.
  • 0: Enables the soft CPU Dynamic Reconfiguration controller internally within the IP
  • 1: Enables external hardware reconfiguration.
Parameter Settings: 10G/25G Ethernet Protocol, CPRI, 25G Ethernet to CPRI Protocol, and 100G Ethernet Protocol (The parameters below are available in both tabs)
Specify Number of Channels 1 Specify the number of channels. The valid number of channels is 1 and this parameter is not selectable.
Note: This parameter is not available in the 100G Ethernet protocol.
Select Board
  • Intel Agilex F-Series Transceiver-SoC Development Kit
  • Other Development Kits
Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is not available, there is no supported board for the options that you select.

Other Development Kits: This option allows the design example to be tested on development kits other than 1ST280EY2F55E2VG. You need to set the pin assignments based on the board used to run this design example.

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