Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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6.16.14. ATS Capability Register and ATS Control Register

Table 93.  ATS Capability Register and ATS Control Register - 0x3C4 The lower 16 bits are the ATS Capability Register and the upper 16 bits are the ATS Control Register

Bits

Register Description

Default Value

Access

[15]

Enable bit. When set, the Function can cache translations.

0

RW

[14:5] Reserved. 0

RO

[4:0] Smallest Translation Unit (STU): This value specifies the minimum number of 4096-byte blocks specified in a Translation Completion or Invalidate Request. This is a power of 2 multiplier. The number of blocks is 2STU. A value of 0 indicates one block and a value of 0x1F indicates 231 blocks, or 8 terabyte (TB) total. 0

RW

[15:6] Reserved. 0 RO
[5] Page Aligned Request: If set, indicates the untranslated address is always aligned to a 4096-byte boundary. This bit is hardwired to 1. 1 RO
[4:0] Invalidate Queue Depth: The number of Invalidate Requests that the Function can accept before throttling the upstream connection. If 0, the Function can accept 32 Invalidate Requests. Set in Platform Designer RO

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