Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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6.16.11. TPH Requester Capability Register

Table 90.  TPH Requester Capability Register - 0x304

Bits

Register Description

Default Value

Access

[31:27]

Reserved.

0

RO

[26:16] ST Table Size: Specifies the number of entries in the Steering Tag Table. When set to 0, the table has 1 entry. When set to 1, the table has 2 entries. The maximum table size is 2048 entries when located in the MSI-X table Each entry is 8 bits. Set in Platform Designer

RO

[15:11] Reserved 0

RO

[10:9] ST Table Location: Setting this field indicates if a Steering Tag Table is implemented for this Function. The following encodings are defined:
  • 2b'00: ST Table not present
  • 2'b01: ST Table stored in the TPH Requestor Capability Structure
  • 2'b10: ST values stored in the MSI-X Table in client RAM
  • 2'b11: Reserved
Valid settings are 0 or 2.
Set in Platform Designer

RO

[8] Extended TPH Requester Supported: When set to 1, indicates that the function is capable of generating requests with 16-bit Steering Tags, using TLP Prefix. This bit is permanently set to 0. 0

RO

[7:3]

Reserved.

0

RO

[2]

Device-Specific Mode Supported: A setting of 1 indicates that the function supports the Device-Specific Mode for TPH Steering Tag generation. The client typically choses the Steering Tag values from the ST Table, but is not required to do so.

Set in Platform Designer

RO

[1]

Interrupt Vector Mode Supported: A setting of 1 indicates that the function supports the Interrupt Vector Mode for TPH Steering Tag generation. In the Interrupt Vector Mode, Steering Tags are attached to MSI/MSI-X interrupt requests. The MSI/MSI-X interrupt vector number selects the Steering Tag for each interrupt.

Set in Platform Designer

RO

[0]

No ST Mode Supported: When set to 1, indicates that the function supports the No ST Mode for the generation of TPH Steering Tags. In the No ST Mode, the device must use a Steering Tag value of 0 for all requests.

This bit is hardwired to 1, because all TPH Requesters are required to support the No ST Mode of operation.

1

RO

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