Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents Write Data Mover Status Avalon-ST Source

Table 17.  Write Data Mover Status Avalon-ST Source Interface
Signal Name Direction Description
wrdm_tx_data_o[18+<PFNUM_WIDTH>-1:18] Output These bits contain the function number.
wrdm_tx_data_o[17:0] Output

[17:16] : reserved

[15] : error

[14:12] : application specific

[11:9] : reserved

[8] : priority

[7:0] : descriptor ID

wrdm_tx_valid_o Output Valid status signal.

This interface does not have a ready input. The application logic must always be ready to receive status information for any descriptor that it has sent to the Write Data Mover.

The ready latency does not matter because there is no ready input.

The Write Data Mover copies over the application specific bits in the wrdm_tx_data_o bus from the corresponding descriptor. A set priority bit indicates that the descriptor was from the priority descriptor sink.