Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents PIPE Interface

Refer to the Intel® Stratix® 10 Avalon® -ST and Single Root I/O Virtualization (SR-IOV) Interfaces for PCIe* Solutions User Guide for a description of the signals on the PIPE interface.
Note: Use this interface only in simulations.