Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
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4.4.3. MSI and MSI-X Capabilities

Table 41.  MSI and MSI-X Capabilities 

Parameter

Value

Description

PF0 Enable MSI

On/Off

When On, adds the MSI functionality for PF0.

Address: 0x050, bits [31:16].

MSI-X Capabilities

PF0 Enable MSI-X

On/Off

When On, adds the MSI-X functionality for PF0.

Bit Range

Table size

[10:0]

System software reads this field to determine the MSI-X Table size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is read-only in the MSI-X Capability Structure. Legal range is 0–2047.

Address offset: 0x068, bits [26:16]

Table offset

[31:0]

Points to the base address of the MSI-X Table. The lower 3 bits of the table BAR indicator (BIR) are set to zero by software to form a 64-bit qword-aligned offset. This field is read-only.

Table BAR indicator

[2:0]

Specifies which one of a function’s BARs, located beginning at 0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only. Legal range is 0–5.

Pending bit array (PBA) offset

[31:0]

Used as an offset from the address contained in one of the function’s Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only in the MSI-X Capability Structure. 3

PBA BAR indicator

[2:0]

Specifies which one of a function's Base Address registers, located beginning at 0x10 in Configuration Space, is used to map the MSI-X PBA into memory space. This field is read-only in the MSI-X Capability Structure. Legal range is 0–5.

3 Throughout this user guide, the terms word, DWORD and qword have the same meaning that they have in the PCI Express Base Specification. A word is 16 bits, a DWORD is 32 bits, and a qword is 64 bits.