Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public
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3.2.3.6.1. PCIe Hard IP Reconfiguration

This interface is a way to access the PCIe Hard IP's internal registers and the PCIe configuration registers. It has its own clock and reset signals.

For more details on the signals in this interface, refer to the Intel® Stratix® 10 Avalon® -MM Interface for PCI Express* Solutions User Guide.

Table 27.  PCIe HIP Reconfiguration Interface Signals
Signal Name Direction Description
hip_reconfig_clk Input PCIe Hard IP reconfiguration clock
hip_reconfig_reset Input PCIe Hard IP reconfiguration reset
hip_reconfig_write Input Standard Avalon® -MM interface. For details, refer to the Avalon® Interface Specifications.
hip_reconfig_read Input
hip_reconfig_address[20:0] Input
hip_reconfig_writedata[7:0] Input
hip_reconfig_readdata[7:0] Output
hip_reconfig_waitrequest Output