Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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5.4. Channel Layout and PLL Usage

The following figure shows the channel layout and connection between the Hard Reset Controller (HRC) and PLLs for the Gen3 x16 variant supported by the Intel L-/H-Tile Avalon-MM+ for PCI Express IP. The channel layout is the same for the Avalon® -ST and Avalon® -MM interfaces to the Application Layer.

Note: The Hard Reset Controller drives the lower 16 channels. The eight remaining channels are available for other protocols. Refer to Channel Availability for more information.
Figure 17. Gen3 x16 Variant