Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Document Table of Contents

2.1. Design Components

Figure 4. Block Diagram for the DMA PCIe* Design Example
Note: The DMA design example includes an external DMA controller, which is instantiated outside of the Intel L-/H-Tile Avalon-MM+ for PCI Express IP core. If you are not using the DMA design example, you need to implement your own external DMA controller.

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