Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public
Document Table of Contents

3.2.3.1. Serial Data Interface

This IP core supports 16 lanes.
Table 24.  Serial Data Interface

Signal

Direction

Description

tx_out[15:0]

Output

Transmit serial data output.
rx_in[15:0]

Input

Receive serial data input.

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