Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents Transceiver Reconfiguration

This is an optional interface that users can enable by selecting the Enable Transceiver Dynamic Reconfiguration option from the GUI.
Table 28.  Transceiver Reconfiguration Interface
Signal Name Direction Description
xcvr_reconfig_clk Input Transceiver reconfiguration clock.
xcvr_reconfig_reset Input Transceiver reconfiguration reset.
xcvr_reconfig_write Input

Standard Avalon® -MM interface. For details, refer to the Avalon® Interface Specifications.

xcvr_reconfig_read Input
xcvr_reconfig_address[31:0] Input
xcvr_reconfig_writedata[31:0] Input
xcvr_reconfig_readdata[31:0] Output
xcvr_reconfig_waitrequest Output