3.1. Block Descriptions
The PCIe Hard IP implements the Transaction, Data Link, and Physical layers stack required by the PCI Express* protocol. This stack allows the user application logic in the Intel® Stratix® 10 FPGA to interface with another device via a PCI Express* link.
While the PCIe* Hard IP uses a 500 MHz clock, other modules in the Bridge use a 250 MHz clock. The Width and Rate Adapter handles the necessary conversion between these two clock domains. An additional adapter converts between the embedded header format of the PCIe Hard IP and the separate header and data format used by the other modules in the Avalon® -MM Bridge.
The Avalon® -MM Bridge mainly consists of four leaf modules that interact with an Avalon® -ST Scheduler. The four leaf modules are:
- Bursting Master: This module converts memory read and write TLPs received over the PCIe link into Avalon® -MM burst read and write transactions, and sends back CplD TLPs for read requests it receives.
- Bursting Slave: This module converts Avalon-MM read and write transactions into PCIe memory read and write TLPs to be transmitted over the PCIe link. This module also processes the CplD TLPs received for the read requests it sent.
- Write Data Mover: This module uses PCIe memory write TLPs and Avalon® -MM read transactions to move large amounts of data from your application logic in the Avalon® -MM space to the system memory in the PCIe space.
- Read Data Mover: This module uses PCIe memory read TLPs and Avalon® -MM write transactions to move large amounts of data from the system memory in the PCIe space to the FPGA memory in the Avalon® -MM space.
The Avalon® -ST Scheduler serves two main functions. In the receive direction, this module distributes the received TLPs to the appropriate leaf module based on the TLP’s type, address and tag. In the transmit direction, this module takes TLPs ready for transmission from the leaf modules and schedules them for transfer to the Width and Rate Adapter to be forwarded to the PCIe Hard IP, based on the available credits. These data transfers follow the PCI Express* Specifications' ordering rules to avoid deadlocks.
Descriptors provided to the Data Movers through one of their Avalon® -ST sink interfaces control the data transfers. The Data Movers report the transfers’ status through their Avalon® -ST source interfaces.
The Config Slave converts single-cycle, 32-bit Avalon® -MM read and write transactions into PCIe configuration read and write TLPs (CfgRd0, CfgRd1, CfgWr0 and CfgWr1) to be sent over the PCIe link. This module also processes the completion TLPs (Cpl and CplD) it receives in return.
The Response Reordering module assembles and reorders completion TLPs received over the PCIe link for the Bursting Slave and the Read Data Mover. It routes the completions based on their tag (see Tags for tag allocation information).
No re-ordering is necessary for the completions sent to the Config module as it only issues one request TLP at a time.
You can individually enable or disable the Bursting Master and Slave, and the Read and Write Data Mover modules by making GUI selections in any combination in the Parameters Editor inside the Intel® Quartus® Prime Pro Edition.
Endpoint applications typically need the Bursting Master to enable the host to provide information for the other modules.
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