Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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3.2.2. Clocks and Resets

The Intel L-/H-Tile Avalon-MM+ for PCI Express IP generates the 250 MHz Application clock, coreclkout_hip and the reset signal. This IP core also provides a synchronized version of the reset signal, app_nreset_status, to the Application. This is an active low reset.

Figure 13.  Intel L-/H-Tile Avalon-MM+ for PCI Express IP Clock and Reset Connections
Table 21.  Application Layer Clock Frequency

Link Width

Maximum Link Rate

Avalon Interface Width





250 MHz

Table 22.  Clocks
Signal Name Direction Description
refclk Input 100 MHz reference clock defined by the PCIe specification. To meet the PCIe* 100ms wake-up time requirement, this clock must be free-running.
Note: This input reference clock must be stable and free-running at device power-up for a successful device configuration.
serdes_pll_locked Output Asserted when coreclkout_hip is stable.
coreclkout_hip Output 250 MHz application clock generated internally to the Intel L-/H-Tile Avalon-MM+ for PCI Express IP. If your application logic does not use coreclkout_hip as the clock, you must insert clock-crossing logic between your application logic and the Intel L-/H-Tile Avalon-MM+ for PCI Express IP.
Table 23.  Resets
Signal Name Direction Clock Description
pin_perst Input Asynchronous This is an active-low input to the PCIe Hard IP, and implements the PERST# function defined by the PCIe specification.
npor Input Asynchronous, edge-sensitive

This active-low warm reset signal is an input to the PCIe Hard IP, and resets the entire PCIe Hard IP. It should be held for a minimum of 20 ns.

This signal is edge-sensitive, not level-sensitive.

app_nreset_status Output app_clk This active-low signal is held high until the PCIe Hard IP is ready. It is only deasserted after npor and pin_perst are deasserted and the PCIe Hard IP has come out of reset.
link_req_rst_n Output hip_clk

The PCIe Hard IP asserts this active-low signal when it is about to go into reset.

When this signal is asserted, the Intel L-/H-Tile Avalon-MM+ for PCI Express IP resets all its PCIe-related registers and queues, including anything related to tags. It stops sending packets to the PCIe Hard IP until the Bus Master Enable bit is set again, and ignores any packet received from the PCIe Hard IP.

ninit_done Input Asynchronous A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode.
Note: To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Intel L-/H-Tile Avalon-MM+ for PCI Express IP. For more details on how you can use the ninit_done signal, refer to Intel® Stratix® 10 Configuration User Guide.