Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Document Table of Contents

1.5. Resource Utilization

For soft IP—Consult with Marketing for a list of configurations that they consider the most important. Round the numbers for ALMs and logic registers up to the nearest 50.

For hard IP—list resource utilization for any bridge or wrapper that is necessary to interface to the IP. Include the following statement:

The following table shows the typical device resource utilization for selected configurations using version 18.0 of the Intel® Quartus® Prime Pro Edition software. The number of ALMs and logic registers are rounded up to the nearest 50. The number stated for M20K memory blocks includes no rounding.

Note: The resource utilization numbers in the following table are for the three variations of the available Gen3 x16 design example: DMA, BAS, and PIO. For more details on the design example and these variations, refer to the chapter Design Example and Test Bench.
Table 4.  Resource Utilization


M20K Memory Blocks

Logic Registers

DMA 57,099 571 119,054
BAS 45,236 485 91,154
PIO 36,754 384 72,365

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