Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents

4.7. Example Designs

Table 46.  Example Designs




Currently Selected Example Design

The generated example design is based on parameterization.

If you enable either/both of the Read Data Mover and Write Data Mover, the generated example design is a DMA design, which includes a direct memory access application. This application includes upstream and downstream transactions.

Otherwise, if you enable the Bursting Slave option, the generated design example is a Bursting Avalon® -MM Slave (BAS) design.

If you do not enable either of the options above, the generated design example is a PIO design.

Simulation On/Off When On, the generated output includes a simulation model.
Select simulation Root Complex BFM


Third-party BFM

The Intel FPGA Root Complex BFM does not support Gen3 x16. Using this BFM makes the design downtrain to Gen3 x8.

Synthesis On/Off When On, the generated output includes a synthesis model.
Generated HDL format


Only Verilog HDL is available in the current release.

Target Development Kit


Intel® Stratix® 10 GX H-Tile Production FPGA Development Kit

Intel® Stratix® 10 MX H-Tile Production FPGA Development Kit

Select the appropriate development board.

If you select one of the development boards, system generation overwrites the device you selected with the device on that development board.
Note: If you select None, system generation does not make any pin assignments. You must make the assignments in the .qsf file.