Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents

2.3. Generating the Design Example

Figure 6. Procedure
  1. In the Intel® Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard).
  2. Specify the Directory, Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings under Family, select Intel® Stratix® 10 (GX/SX/MX/TX) and the Target Device for your design. Note that the selected device is only used if you select None in Step 10e below.
  6. Click Finish.
  7. In the IP Catalog locate and add the Intel L-/H-Tile Avalon-MM+ for PCI Express IP.
  8. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  9. On the IP Settings tabs, specify the parameters for your IP variation.
  10. On the Example Designs tab, make the following selections:
    1. For Available Example Designs, select DMA.
    2. For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
    3. For Select simulation Root Complex BFM, choose the appropriate BFM:
    4. For Generated HDL Format, only Verilog is available in the current release.
    5. For Target Development Kit, select the appropriate option.
      Note: If you select None, the generated design example targets the device specified. Otherwise, the design example uses the device on the selected development board. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file.
  11. Select Generate Example Design to create a design example that you can simulate and download to hardware. If you select one of the Intel® Stratix® 10 development boards, the device on that board supersedes the device previously selected in the Intel® Quartus® Prime Pro Edition project if the devices are different. When the prompt asks you to specify the directory for your example design, you can choose to accept the default directory, <example_design>/avmm_bridge_512_0_example_design
    Figure 7. Example Design Tab
    When you generate an Intel® Stratix® 10 example design, a file called recommended_pinassignments_s10.txt is created in the directory avmm_bridge_512_0_example_design. 1
  12. Click Finish to close the dummy .ip file, which does not have the complete configuration.
  13. Click No upon receiving the prompt, Recent changes have not been generated. Generate now? since you do not need to generate any file for the design associated with the dummy .ip file.
  14. Change directory to the example design directory. Open pcie_example_design.qpf in Intel® Quartus® Prime Pro Edition.
  15. Start compilation. This generates the .sof file for the complete example design, which you can download to a board to perform hardware verification.
  16. Close your project.
1 This file contains the recommended pin assignments for all the pins in the example design. If you chose a GX, SX or MX development kit option in the pull-down menu for Target Development Kit, the pin assignments in the recommended_pinassignments_s10.txt file match those that are in the .qsf file in the same directory. If you chose NONE in the pull-down menu, the .qsf file does not contain any pin assignment. In this case, you can copy the pin assignments in the recommended_pinassignments_s10.txt file to the .qsf file. You can always change any pin assignment in the .qsf file to satisfy your design or board requirements.