3.2.3. System Interfaces
TX and RX Serial Data
This differential, serial interface is the physical link between a Root Port and an Endpoint. This IP Core supports 16 lanes, and operates in Gen3 at 8 GT/s. Each lane includes a TX and RX differential pair. Data is striped across all available lanes.
This is a parallel interface between the PCIe IP Core and PHY. The PIPE data bus is 32 bits. Each lane includes four control/data bits and other signals. It carries the TLP data before it is serialized. It is available for simulation only and provides more visibility for debugging.
Legacy interrupts, MSI, and MSI-X interrupts are all controlled and generated externally to the Intel L-/H-Tile Avalon-MM+ for PCI Express IP to ensure total flexibility in allocating interrupt resources based on the needs of the application.
The host can initiate an MSI by including a descriptor for an immediate write at the end of the descriptor table that it places in system memory. When the Write Data Mover receives this descriptor on one of its descriptor queues, it can perform the memory write to send the MSI because the necessary MSI information (address and data) is contained in the descriptor itself.
The user application logic in the Avalon® -MM space can also initiate an MSI by leveraging the Bursting Avalon® Slave (BAS) interface.
Hard IP ReconfigurationThis optional Avalon® -MM interface allows you to dynamically update the value of read-only configuration registers at run-time. It is available when Enable HIP dynamic reconfiguration of PCIe read-only registers is enabled in the component GUI.
Hard IP Status and Link Training
This optional interface includes the following signals that are useful for debugging
- Link status signals
- Interrupt status signals
- TX and RX parity error signals
- Correctable and uncorrectable error signals
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