Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public
Document Table of Contents
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3.2.1.2.1. Write Data Mover Avalon-MM Read Master and Conduit

Table 14.  Write Data Mover Avalon-MM Read Master and Conduit Interface
Signal Name Direction Description
wrdm_pfnum_o[<PFNUM_WIDTH>-1:0] Output Avalon conduit showing function number.
wrdm_waitrequest_i Input

Standard Avalon® -MM Read Master interface. For details, refer to the Avalon® Interface Specifications.

Byte enables are all ones for bursts larger than one cycle.

wrdm_read_o Output
wrdm_address_o[63:0] Output
wrdm_burstcount_o[3:0] Output
wrdm_byteenable_o[63:0] Output
wrdm_readdatavalid_i Input
wrdm_readdata_i[511:0] Input
wrdm_response_i[1:0] Input

The waitrequestAllowance of this interface is four.