Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public
Document Table of Contents
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2.8. Ensuring the Design Example Meets Timing Requirements

If the generated design example fails to meet the timing requirements necessary to operate at 250 MHz, add pipeline registers to the design by performing the following steps:

  1. Open the system in Platform Designer.
  2. On the Menu bar, choose System, and then Show System with Platform Designer Interconnect. This opens another window.
  3. In the new window, select the Memory-Mapped Interconnect tab. There is an option in the bottom left corner to Show Pipelinable Locations. Check that box. This shows locations where you can add pipeline registers.
  4. Check your timing report to see where you need to add pipeline registers to achieve timing closure for your paths.
  5. Right click where you want to add a pipeline register and check the Pipelined box. A pipeline register appears at that location. Repeat this step at all locations where you want to add pipeline registers.
  6. Save and regenerate the system.
  7. In the main window, click on the Interconnect Requirements tab. You can see the pipeline stages there.