Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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A.1.1. Simulation Fails to Progress Beyond Polling.Active State

If your PIPE simulation cycles between the Detect.Quiet (6'h00), Detect.Active (6'h01), and Polling.Active (6'h02) LTSSM states, the PIPE interface width may be incorrect. The width of the DUT top-level PIPE interface is 32 bits for Intel® Stratix® 10 devices.

Table 66.  Changes for 32-Bit PIPE Interface
8-Bit PIPE Interface 32-Bit PIPE Interface
output wire [7:0] pcie_s10_hip_0_hip_pipe_txdata0 output wire [31:0] pcie_s10_hip_0_hip_pipe_txdata0
input wire [7:0] pcie_s10_hip_0_hip_pipe_rxdata0 input wire [31:0] pcie_s10_hip_0_hip_pipe_rxdata0
output wire pcie_s10_simulation_inst_pcie_s10_hip_0_hip_pipe_txdatak0 output wire [3:0] pcie_s10_simulation_inst_pcie_s10_hip_0_hip_pipe_txdatak0
input wire pcie_s10_simulation_inst_pcie_s10_hip_0_hip_pipe_rxdatak0 input wire [3:0] pcie_s10_simulation_inst_pcie_s10_hip_0_hip_pipe_rxdatak0