Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents

1.6. Transceiver Tiles

Intel® Stratix® 10 introduces several transceiver tile variants to support a wide variety of protocols.
Figure 1.  Intel® Stratix® 10 Transceiver Tile Block Diagram
Table 5.  Transceiver Tiles Channel Types
Tile Device Type Channel Capability Channel Hard IP Access
Chip-to-Chip Backplane
L-Tile GX/SX 26 Gbps (NRZ) 12.5 Gbps (NRZ) PCIe Gen3x16
H-Tile GX/SX/MX/TX 28.3 Gbps (NRZ) 28.3 Gbps (NRZ) PCIe Gen3x16
Note: E-Tiles do not include any PCIe Hard IP block and do not support PCIe, so they are not discussed in this document.

L-Tile and H-Tile

Both L and H transceiver tiles contain four transceiver banks-with a total of 24 duplex channels, eight ATX PLLs, eight fPLLs, eight CMU PLLs, a PCIe Hard IP block, and associated input reference and transmitter clock networks. L and H transceiver tiles also include 10GBASE-KR/40GBASE-KR4 FEC block in each channel.

L-Tiles have transceiver channels that support up to 26 Gbps chip-to-chip or 12.5 Gbps backplane applications. H-Tiles have transceiver channels to support 28.3 Gbps applications. H-Tile channels support fast lock-time for Gigabit-capable passive optical network (GPON).

Only Intel® Stratix® 10 GX/SX devices support L-Tiles, while most of the product line supports H-Tiles. Package migration is available with Intel® Stratix® 10 GX/SX from L-Tile to H-Tile variants.