Visible to Intel only — GUID: jqj1520633313570
Ixiasoft
Visible to Intel only — GUID: jqj1520633313570
Ixiasoft
4.2. Base Address Registers
Parameter |
Value |
Description |
---|---|---|
BAR0 Type |
Disabled 64-bit prefetchable memory 32-bit non-prefetchable memory |
If you select 64-bit prefetchable memory, 2 contiguous BARs are combined to form a 64-bit prefetchable BAR; you must set the higher numbered BAR to Disabled. A non-prefetchable 64‑bit BAR is not supported because in a typical system, the maximum non-prefetchable memory window is 32 bits. Defining memory as prefetchable allows contiguous data to be fetched ahead. Prefetching memory is advantageous when the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:
|
BAR1 Size | 256 Bytes – 8 EBytes |
Specifies the size of the address space accessible to the BAR. |
BAR2 Size | 256 Bytes – 8 EBytes |
Specifies the size of the address space accessible to the BAR. |
BAR3 Size | 256 Bytes – 8 EBytes |
Specifies the size of the address space accessible to the BAR. |
BAR4 Size | 256 Bytes – 8 EBytes |
Specifies the size of the address space accessible to the BAR. |
BAR5 Size | 256 Bytes – 8 EBytes |
Specifies the size of the address space accessible to the BAR. |
BAR1 Type |
Disabled 32-bit non-prefetchable memory |
|
BAR2 Type |
Disabled 64-bit prefetchable memory 32-bit non-prefetchable memory |
|
BAR3 Type |
Disabled 32-bit non-prefetchable memory |
|
BAR4 Type |
Disabled 64-bit prefetchable memory 32-bit non-prefetchable memory |
|
BAR5 Type |
Disabled 32-bit non-prefetchable memory |
Did you find the information on this page useful?
Feedback Message
Characters remaining: