Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents Interrupts

The Intel L-/H-Tile Avalon-MM+ for PCI Express IP does not use the interrupt-related signals described in the next section. However, the user application logic can use them to generate or respond to interrupts.