Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Document Table of Contents Configuration Output Interface

The Transaction Layer (TL) bus provides a subset of the information stored in the Configuration Space. Use this information in conjunction with the app_err* signals to understand TLP transmission problems.
Table 26.  Configuration Output Interface Signals
Signal Direction Description

tl_cfg_add[3:0] (H-tile)

tl_cfg_add[4:0] (L-tile)

Output Address of the TLP register. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl[31:0].
tl_cfg_ctl[31:0] Output The tl_cfg_ctl signal is multiplexed and contains a subset of contents of the Configuration Space registers.
tl_cfg_func[1:0] Output Specifies the function whose Configuration Space register values are being driven onto tl_cfg_ctl. The following encodings are defined:
  • 2'b00: Physical Function (PF0)
  • 2'b01: PF1 for H-tile, reserved for L-tile
  • 2'b10: PF2 for H-tile, reserved for L-tile
  • 2'b11: PF3 for H-tile, reserved for L-tile

Information on the tl_cfg_ctl bus is time-division multiplexed (TDM). Examples of information multiplexed onto the tl_cfg_ctl bus include device number, bus number, MSI information (address, data, mask) and AER information. For more details, refer to the Transaction Layer Configuration Space Interface section of the Intel® Stratix® 10 Avalon® streaming and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express Solutions User Guide.

Note: In the 20.3 release of Intel® Quartus® Prime, the configuration output interface (tl_cfg_*) is exported by default.

Did you find the information on this page useful?

Characters remaining:

Feedback Message