F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
|Document Version||Intel® Quartus® Prime Version||Changes|
|2021.10.19||21.1||Changed the device support level for Intel® Stratix® 10 to Final Support in the Device Family Support section.|
Added an Appendix chapter on Root Port enumeration.
Added a note to the Features section stating that L- and H-tile Avalon® Memory-mapped+ IP for PCI Express only supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS).
|2021.01.11||20.4||Added a figure of a sample descriptor table to the Programming Model for the Example Design section.|
Removed the Multi-function and Function-Level Reset (FLR) parameters from the Parameters chapter since these features are not available.
Added descriptions for the signals in the Bus Master Enable (BME) conduit to the System Interfaces section.
Updated the IP name to Intel L-/H-tile Avalon® Memory-mapped+ IP for PCI Express* .
Added descriptions for the tl_cfg_* signals to the Configuration Output Interface section.
|2020.06.03||19.4||Added the description for the new input ninit_done to the Clocks and Resets section. Also added a link to AN 891: Using the Reset Release Intel FPGA IP, which describes the Reset Release IP that is used to drive the ninit_done input.|
Updated the document title to Avalon® memory mapped Intel® Stratix® 10 Hard IP+ for PCI Express* Solutions User Guide to meet new legal naming guidelines.
Fixed a typo in the byte address of some Reserved bits in Table 49. Correspondence between Configuration Space Capability Structures and the PCIe Base Specification Description.
|2019.11.05||19.3||Changed the maximum BAR size to 8 EBytes in the Base Address Registers section.|
Added a note to clarify that this User Guide is applicable to H-Tile and L-Tile variants of the Intel® Stratix® 10 devices only.
Changed the device family support level to Preliminary.
Added the Autonomous Hard IP mode to the Features list.
Updated the Figure Example of Interrupt Controller Integration with Endpoint Avalon® -MM Intel® Stratix® 10 Hard IP+ for PCIe to replace the msi_* signals with tl_cfg_* signals.
|2019.07.19||19.1||Added descriptions for int_status[10:8] (available for H-Tile only).|
Added a note stating that refclk must be stable and free-running at device power-up for a successful device configuration.
Added descriptions for the int_status[7:0] and int_status_common[2:0] interface signals in the Hard IP Status and Link Training Conduit section.
Reworded some sections to clarify that this IP core does not include an internal DMA controller. It only contains a BAR Interpreter and Data Movers. The DMA design example does include an external DMA controller. If you are not using the DMA design example, you need to implement your own external DMA controller.
Changed the term Descriptor Controller to DMA Controller.
Clarified that bam_response_i[1:0] are reserved inputs and should be driven to 0.
|2019.03.05||18.1.1||Updated the simulation commands in the Simulating the Design Example section.|
|2019.01.16||18.1.1||Removed the section on BIOS enumeration issues because it is not applicable to Intel® Stratix® 10 devices.|
Added the completion timeout checking feature.
Added the PCIe Link Inspector overview.
|2018.10.31||18.1||Added the channel layout figure to the Channel Layout and PLL Usage section.|
Added descriptions for two new signal busses, flr_pf_active_o[<PFNUM> - 1 : 0] and flr_pf_done_i[<PFNUM> -1 : 0].
Updated the steps to run ModelSim simulations for a design example.
Updated the steps to run a design example.
|2018.08.29||18.0||Added the step to invoke vsim to the instructions for running ModelSim simulations.|
Did you find the information on this page useful?