1. Introduction 2. Quick Start Guide 3. Block and Interface Descriptions 4. Parameters 5. Designing with the IP Core 6. Registers 7. Design Example and Testbench A. Troubleshooting and Observing the Link B. Avalon-MM IP Variants Comparison C. Root Port BFM D. BFM Procedures and Functions E. Root Port Enumeration F. Document Revision History for Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide
2.1. Design Components 2.2. Directory Structure 2.3. Generating the Design Example 2.4. Simulating the Design Example 2.5. Compiling the Design Example and Programming the Device 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example Application 2.8. Ensuring the Design Example Meets Timing Requirements
6.1.1. Register Access Definitions 6.1.2. PCI Configuration Header Registers 6.1.3. PCI Express Capability Structures 6.1.4. Intel Defined VSEC Capability Header 6.1.5. Uncorrectable Internal Error Status Register 6.1.6. Uncorrectable Internal Error Mask Register 6.1.7. Correctable Internal Error Status Register 6.1.8. Correctable Internal Error Mask Register
D.1. ebfm_barwr Procedure D.2. ebfm_barwr_imm Procedure D.3. ebfm_barrd_wait Procedure D.4. ebfm_barrd_nowt Procedure D.5. ebfm_cfgwr_imm_wait Procedure D.6. ebfm_cfgwr_imm_nowt Procedure D.7. ebfm_cfgrd_wait Procedure D.8. ebfm_cfgrd_nowt Procedure D.9. BFM Configuration Procedures D.10. BFM Shared Memory Access Procedures D.11. BFM Log and Message Procedures D.12. Verilog HDL Formatting Functions
The Intel L-/H-Tile Avalon-MM+ for PCI Express IP supports the following features:
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a hard IP.
- Support for Gen3 x16 for Endpoints.
- Support for 512-bit Avalon-MM interface to the Application Layer at the Gen3 x16 data rate for Intel® Stratix® 10 devices.
- Support for address widths ranging from 10-bit to 64-bit for the Avalon-MM interface to the Application Layer.
- Platform Designer design example demonstrating parameterization, design modules, and connectivity.
- Standard Avalon® -MM interfaces:
- High-throughput bursting Avalon® -MM slave with byte enable support.
- High-throughput bursting Avalon® -MM master with byte enable support associated with 1 - 7 Base Address Registers (BARs).
- High-throughput data movers for DMA support:
- Moves data from local memory in Avalon® -MM space to system memory in PCIe* space using PCIe* Memory Write (MWr) Transaction Layer Packets (TLPs).
- Moves data from system memory in PCIe* space to local memory in Avalon® -MM space using PCIe* Memory Read (MRd) TLPs.
- The Intel L-/H-Tile Avalon-MM+ for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS)
- Support for legacy interrupts (INTx), Message Signaled Interrupts (MSI) and MSI-X.
- Advanced Error Reporting (AER): In Intel® Stratix® 10 devices, Advanced Error Reporting is always enabled in the PCIe Hard IP for both the L and H transceiver tiles.
- Completion timeout checking.
- Modular implementation to select the required features for a specific application:
- Simultaneous support for data movers and high-throughput Avalon® -MM slaves and masters.
- Avalon® -MM slave to easily access the entire PCIe* address space without requiring any PCIe* specific knowledge.
- Autonomous Hard IP mode, allowing the PCIe IP core to begin operation before the FPGA fabric is programmed. This mode is enabled by default. It cannot be disabled.
Note: Unless Readiness Notifications mechanisms are used (see Section 6.23 of the PCIe Base Specification), the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device which fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
- Available in Intel® Quartus® Prime Pro Edition, in both Platform Designer and IP Catalog.
- Operates at 250 MHz in -1 or -2 speed grade Intel® Stratix® 10 devices.
- Easy to use:
- No license requirement.
Note: For a list of differences between this Intel L-/H-Tile Avalon-MM+ for PCI Express IP and the Intel L-/H-Tile Avalon-MM for PCI Express IP (which can support configurations up to Gen3 x8), refer to the Avalon® -MM IP Variants Comparison section in the Appendix.
Note: Throughout this document, the term Avalon® -MM Hard IP+ for PCI Express may also be used to refer to the Intel L-/H-Tile Avalon-MM+ for PCI Express IP.
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