Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents

1.1. Features

The Intel L-/H-Tile Avalon-MM+ for PCI Express IP supports the following features:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a hard IP.
  • Support for Gen3 x16 for Endpoints.
  • Support for 512-bit Avalon-MM interface to the Application Layer at the Gen3 x16 data rate for Intel® Stratix® 10 devices.
  • Support for address widths ranging from 10-bit to 64-bit for the Avalon-MM interface to the Application Layer.
  • Platform Designer design example demonstrating parameterization, design modules, and connectivity.
  • Standard Avalon® -MM interfaces:
    • High-throughput bursting Avalon® -MM slave with byte enable support.
    • High-throughput bursting Avalon® -MM master with byte enable support associated with 1 - 7 Base Address Registers (BARs).
  • High-throughput data movers for DMA support:
    • Moves data from local memory in Avalon® -MM space to system memory in PCIe* space using PCIe* Memory Write (MWr) Transaction Layer Packets (TLPs).
    • Moves data from system memory in PCIe* space to local memory in Avalon® -MM space using PCIe* Memory Read (MRd) TLPs.
  • The Intel L-/H-Tile Avalon-MM+ for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS)
  • Support for legacy interrupts (INTx), Message Signaled Interrupts (MSI) and MSI-X.
  • Advanced Error Reporting (AER): In Intel® Stratix® 10 devices, Advanced Error Reporting is always enabled in the PCIe Hard IP for both the L and H transceiver tiles.
  • Completion timeout checking.
  • Modular implementation to select the required features for a specific application:
    • Simultaneous support for data movers and high-throughput Avalon® -MM slaves and masters.
    • Avalon® -MM slave to easily access the entire PCIe* address space without requiring any PCIe* specific knowledge.
  • Autonomous Hard IP mode, allowing the PCIe IP core to begin operation before the FPGA fabric is programmed. This mode is enabled by default. It cannot be disabled.
    Note: Unless Readiness Notifications mechanisms are used (see Section 6.23 of the PCIe Base Specification), the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device which fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • Available in Intel® Quartus® Prime Pro Edition, in both Platform Designer and IP Catalog.
  • Operates at 250 MHz in -1 or -2 speed grade Intel® Stratix® 10 devices.
  • Easy to use:
    • No license requirement.
Note: For a list of differences between this Intel L-/H-Tile Avalon-MM+ for PCI Express IP and the Intel L-/H-Tile Avalon-MM for PCI Express IP (which can support configurations up to Gen3 x8), refer to the Avalon® -MM IP Variants Comparison section in the Appendix.
Note: Throughout this document, the term Avalon® -MM Hard IP+ for PCI Express may also be used to refer to the Intel L-/H-Tile Avalon-MM+ for PCI Express IP.