Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public

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4.3. Device Identification Registers

The following table lists the default values of the read-only registers in the PCI* Configuration Header Space. You can use the parameter editor to set the values of these registers. At run time, you can change the values of these registers using the optional Hard IP Reconfiguration block signals.

Table 38.   PCI* Header Configuration Space Registers

Register Name

Default Value

Description

Vendor ID

0x1172

Sets the read-only value of the Vendor ID register. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification.

Address offset: 0x000, bits [15:0].

Device ID

0x0000

Sets the read-only value of the Device ID register.

Address offset: 0x000, bits [31:16].

Revision ID

0x01

Sets the read-only value of the Revision ID register.

Address offset: 0x008, bits [7:0].

Class code

0xFF0000

Sets the read-only value of the Class Code register.

Address offset: 0x008, bits [31:8].

Subsystem Vendor ID

0x0000

Sets the read-only value of Subsystem Vendor ID register in the PCI Type 0 Configuration Space. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification. This value is assigned by PCI-SIG to the device manufacturer. This value is only used in Root Port variants.

Address offset: 0x02C, bits [15:0].

Subsystem Device ID

0x0000

Sets the read-only value of the Subsystem Device ID register in the PCI Type 0 Configuration Space. This value is only used in Root Port variants.

Address offset: 0x02C, bits [31:16].