Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public
Document Table of Contents
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7.1.1.2.1. Register Set

The registers in the Traffic Generator are 32-bit wide.

Table 63.  Register Set
Offset Name Description
0x00 RAdd Read start address
0x04 RCnt Read count
0x08 RErr Read error count
0x0C RCtl Read control
0x10 WAdd Write start address
0x14 WCnt Write count
0x18 WErr Reserved (Write error detection not available yet)
0x1C WCtl Write control

The RAdd and WAdd registers contain the base addresses that the Traffic Generator reads from and writes to respectively. These are byte addresses and must be Avalon® -MM word aligned (i.e. bits [5:0] are assumed to be set to 0).

Write to the RCnt and WCnt registers to specify the number of transfers to execute. Writing a 0 to these registers means non-stop transfers. Reading from one of these registers returns the number of transfers that have occurred since it was last read.

Reading the RErr register returns the number of errors detected since the register was last read. A maximum of one error is counted per clock cycle. Because the write error detection feature is not available yet, you cannot get a valid number of errors by reading the WErr register.

The RCtl and WCtl registers contain fields that define various aspects of the transfers, and start and stop the transfers.

Table 64.  RCtl and WCtl Register Bits Descriptions
Bits Name Description
[3:0] target_size

Size of the area of memory to read or write

0: 1 KB

1: 2 KB

2: 4 KB

3: 8 KB

4: 16 KB

5: 32 KB

6: 64 KB

7: 128 KB

8: 256 KB

9: 512 KB

10: 1 MB

11 - 15: Reserved

[7:4] transfer_size

Size of transfers

0: 1 byte

1: 2 bytes

2: 1 dword (4 bytes)

3: 2 dwords (8 bytes)

4: 4 dwords (16 bytes)

5: 8 dwords (32 bytes)

6: 16 dwords (1 cycle - 64 bytes)

7: 32 dwords (2 cycles - 128 bytes)

8: 48 dwords (3 cycles - 192 bytes)

9: 64 dwords (4 cycles - 256 bytes)

10: 80 dwords (5 cycles - 320 bytes)

11: 96 dwords (6 cycles - 384 bytes)

12: 112 dwords (7 cycles - 448 bytes)

13: 128 dwords (8 cycles - 512 bytes)

14: 16 dwords (2 cycles - 64 bytes). Start at 32 bytes offset from the specified address.

15: Reserved

[30:8] reserved Reserved
31 enable

0: stop

1: start

All addresses are read or written sequentially. For example, if the transfer size is one byte and the first target byte address is N, the second transfer targets byte address N+1 (using the appropriate byte enable). If the transfer size is 48 dwords and the first target byte address is N, the second transfer targets byte address N + 192.

If the number of transfers multiplied by the transfer size is larger than the target area (or if the transfers are non-stop), the transfers loop back to the beginning of the target area when they reach its end. For transfer sizes that are not a power of two, the exact behavior at wraparound is not specified. The Traffic Checker detects one error every time the transfers loop back to the beginning of the target area.

The target_size parameter should not exceed the size of one address mapping window, or at least should not exceed the size of the address mapping table.