Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Public

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3.2.3.7. Hard IP Status and Link Training Conduit

The following signals are provided for debug and monitoring purposes. They come directly from the PCIe HIP, and are in the hip_clk clock domain.
Table 31.  PCIe HIP Status and Link Training Conduit Signals
Signal Name Direction Description
link_up_o Output When asserted, this signal indicates that the link is up.
ltssmstate_o[5:0] Output

These are the state variables for the LTSSM state machine. Their encoding defines the following states:

6'h00 : DETECT_QUIET

6'h01 : DETECT_ACT

6'h02 : POLL_ACTIVE

6'h03 : POLL_COMPLIANCE

6'h04 : POLL_CONFIG

6'h05 : PRE_DETECT_QUIET

6'h06 : DETECT_WAIT

6'h07 : CFG_LINKWD_START

6'h08 : CFG_LINKWD_ACCEPT

6'h09 : CFG_LANENUM_WAIT

6'h0A : CFG_LANENUM_ACCEPT

6'h0B : CFG_COMPLETE

6'h0C : CFG_IDLE

6'h0D : RCVRY_LOCK

6'h0E : RCVRY_SPEED

6'h0F : RCVRY_RCVRCFG

6'h10 : RCVRY_IDLE

6'h20 : RCVRY_EQ0

6'h21 : RCVRY_EQ1

6'h22 : RCVRY_EQ2

6'h23 : RCVRY_EQ3

6'h11 : L0

6'h12 : L0S

6'h13 : L123_SEND_EIDLE

6'h14 : L1_IDLE

6'h15 : L2_IDLE

6'h16 : L2_WAKE

6'h17 : DISABLED_ENTRY

6'h18 : DISABLED_IDLE

6'h19 : DISABLED

6'h1A : LPBK_ENTRY

6'h1B : LPBK_ACTIVE

6'h1C : LPBK_EXIT

6'h1D : LPBK_EXIT_TIMEOUT

6'h1E : HOT_RESET_ENTRY

6'h1F : HOT_RESET

currentspeed_o[1:0] Output

These signals indicate the current speed of the PCIe link. The following encodings are defined:

2'b00 : Undefined

2'b01 : Gen1

2'b10 : Gen2

2'b11 : Gen3

lane_act_o[4:0] Output

These signals indicate the number of lanes that are configured during link training. The following encodings are defined:

5'b0 0001 : 1 lane

5'b0 0010 : 2 lanes

5'b0 0100 : 4 lanes

5'b0 1000 : 8 lanes

5'b1 0000 : 16 lanes

int_status[10:0] (H-Tile)

int_status[7:0] (L-Tile)

Output
The int_status[3:0] signals drive legacy interrupts to the application.
  • int_status[0]: Interrupt signal A
  • int_status[1]: Interrupt signal B
  • int_status[2]: Interrupt signal C
  • int_status[3]: Interrupt signal D
The int_status[10:4] signals provide status for other interrupts.
  • int_status[4]: Specifies a Root Port AER error interrupt. This bit is set when the cfg_aer_rc_err_msi or cfg_aer_rc_err_int signal asserts. This bit is cleared when software writes 1 to the register bit or when cfg_aer_rc_err_int is deasserted.
  • int_status[5]: Specifies the Root Port PME interrupt status. It is set when cfg_pme_msi or cfg_pme_int asserts. It is cleared when software writes a 1 to clear or when cfg_pme_int deasserts.
  • int_status[6]: Is asserted when a hot plug event occurs and Power Management Events (PME) are enabled. (PMEs are typically used to revive the system or a function from a low power state).
  • int_status[7]: Specifies the hot plug event interrupt status.
  • int_status[8]: Specifies the interrupt status for the Link Autonomous Bandwidth Status register. H-Tile only.
  • int_status[9]: Specifies the interrupt status for the Link Bandwidth Management Status register. H-Tile only.
  • int_status[10]: Specifies the interrupt status for the Link Equalization Request bit in the Link Status register. H-Tile only.
int_status_common[2:0] Output
Specify the interrupt status for the following registers. When asserted, each signal indicates that an interrupt is pending:
  • int_status_common[0]: Autonomous bandwidth status register.
  • int_status_common[1]: Bandwidth management status register.
  • int_status_common[2]: Link equalization request bit in the link status register.