Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Document Table of Contents

6.1.2. PCI Configuration Header Registers

The Correspondence between Configuration Space Registers and the PCIe Specification lists the appropriate section of the PCI Express Base Specification that describes these registers.

Figure 18. Configuration Space Registers Address Map
Figure 19. PCI Configuration Space Registers - Byte Address Offsets and Layout

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