Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021
Document Table of Contents Bus Master Enable (BME) Conduit

Table 32.  BME Conduit Signals

Signal Name





Indicate the status of the bus_master_enable bit (i.e bit 2) in the PCI command register. This bit specifies if a function is capable of issuing Memory and IO Read/Write requests. Refer to the PCIe Specifications for more details.
  • bus_master_enable_o[0] corresponds to function 0.
  • bus_master_enable_o[1] corresponds to function 1.
  • bus_master_enable_o[2] corresponds to function 2.
  • bus_master_enable_o[3] corresponds to function 3.

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