Intel® L- and H-tile Avalon® Memory-mapped+ IP for PCI Express* User Guide

ID 683527
Date 10/19/2021

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Document Table of Contents Bursting Avalon-MM Master (BAM) Interface

The Bursting Avalon® -MM Master module has one user-visible Avalon® -MM Master interface.

The bam_bar_o bus contains the BAR address for a particular TLP. This bus is as an extension of the standard address bus.

Table 20.  Bursting Master Avalon-MM Master and Conduit Interface
Signal Name Direction Description
bam_pfnum_o[PFNUM_WIDTH-1:0] Output

Avalon® conduit showing function number.

bam_bar_o[2:0] Output

000 : Memory BAR 0

001 : Memory BAR 1

010 : Memory BAR 2

011 : Memory BAR 3

100 : Memory BAR 4

101 : Memory BAR 5

110 : Reserved

111 : Expansion ROM BAR

bam_waitrequest_i Input Avalon® -MM wait request signal with waitrequestAllowance of 8.
bam_address_o[BAM_ADDR_WIDTH-1:0] Output

The width of the Bursting Master's address bus is the maximum of the widths of all the enabled BARs.

For BARs narrower than the widest BAR, the address bus' additional most-significant bits are driven to 0.

bam_byteenable_o[63:0] Output

The BAM interface supports all contiguous byteenable patterns.

bam_read_o Output  
bam_readdata_i[511:0] Input  
bam_readdatavalid_i Input  
bam_response_i[1:0] Input

Reserved. Drive these inputs to 0.

bam_write_o Output  
bam_writedata_o[511:0] Output  
bam_burstcount_o[3:0] Output  

For more details on these interface signals, refer to the Avalon® Interface Specifications.